A Seminar on Learning MAX10 FPGA Board

A Seminar on Learning MAX10 FPGA Board and Current R&D in Industry

Electronics Engineering Department organized a seminar on topic “Learning MAX10 FPGA Board  and Current R&D in Industry on 26th March 2018 at Microprocessor Lab for third year Electronics students. Mr. Kiran Jambhale, Alumnus of FAMT, conducted the seminar. Mr Kiran Jambhale is a FPGA Design Engineer in Unizen Technologies, Bangalore.

This seminar was an initiative taken by Mr. Ritesh Belgudri, Alumnus of FAMT, who felt a need to make students aware about a plenty of job opportunities available in VLSI domain, specifically in programming using Verilog and VHDL and implementing a design on FPGA/CPLD. Mr. Ritesh Belgudri is working in this domain for more than three years.

The seminar began by welcome and introducing Mr. Kiran Jambhale by Ms. Shalakha Keer followed by an introductory speech by Prof. G. G. Bhide (HOD Electronics Department). Topics covered in the seminar were basics of FPGA-CPLD, Verilog coding, hardware details of MAX10 FPGA board, using Quartus-II software, Led blink code in Verilog and implementing it on MAX10 FPGA board. Thereafter, Mr. Kiran explained the students about the projects that he had worked on like Digital Stamp, JTI packet printer and ARINK 1553 programmer. He also discussed the projects, the research and development that is on-going in industry. The students interacted with him. The seminar ended with a vote of thanks. Total 28 students participated in the seminar. Miss. V. V. Nimbalkar coordinated the seminar.

423 total views, 3 views today